phynexis-deps/OpenBLAS
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
10,785 Commits 60 Branches 70 Tags
develop
Commit Graph
65 Commits
Author SHA1 Message Date
Martin Kroeker 3f55cbce38 Fix array/pointer argument mismatch on WoA 2026-07-17 14:31:37 +02:00
Martin Kroeker 2a5d33a95d Add part code for NeoverseV3 2026-04-16 14:45:41 +02:00
Martin Kroeker ee70631c4d Add Neoverse V3AE CPUID from NVIDIA Jetson AGX Thor 2026-03-10 22:32:44 +01:00
Martin Kroeker 387be46c42 Support Cortex X925 as NeoverseV2 2026-02-12 00:43:52 +01:00
Martin Kroeker 825d3ad12e AppleClang does not define feature local_streaming 2025-11-28 23:54:16 +01:00
Martin Kroeker b0bd49a064 Add compiler guard around the M4 HAVE_SME property 2025-11-24 22:07:38 +01:00
Martin Kroeker 7d35bf61ba Add cpuid for Apple M5 (from a PR to the archspec project) 2025-11-24 08:21:37 +01:00
Martin Kroeker ea85b6696f Merge branch 'OpenMathLib:develop' into issue5414 2025-11-23 10:14:07 +01:00
Martin Kroeker fa0403bd17 Report proper cache sizes for Qualcomm Oryon in WoA 2025-11-22 18:46:44 +01:00
Martin Kroeker fc516af155 Merge branch 'develop' into issue5414 2025-10-01 14:12:59 -07:00
Martin Kroeker 6798aec462 Any Apple cpu running Linux has to be Vortex 2025-09-25 20:26:47 +02:00
Martin Kroeker 4e2a8c18e5 Split VORTEXM4 from VORTEX target due to SME support 2025-08-18 01:53:04 -07:00
Martin Kroeker ee26caffb3 Merge pull request #5309 from davidz-ampere/dev-ampereone 
Add support for Ampere AmpereOne processors
 2025-06-24 12:27:08 +02:00
davidz-ampere aa90ab4142 Add support for Ampere AmpereOne processors 2025-06-24 00:12:34 -04:00
Masato Nakagawa 1dd396033a Fix:Problem with identifying some ARM64 processors. 2025-06-16 19:50:08 +09:00
davidz-ampere be68ef03b4 Add support for Ampere processors 2025-06-15 22:00:40 -04:00
zanpeeters acef78c778 Reset buffer length before every call to sysctlbyname. 2025-04-15 17:17:17 -07:00
zanpeeters d1c2528aed Add L1_DATA_LINESIZE for ifdef __APPLE__ 2025-04-15 17:14:19 -07:00
zanpeeters 7b66330dea hw.perflevel[01].cpusperl changed to hw.perflevel[01].cpusperl2 2025-04-15 17:12:03 -07:00
Martin Kroeker ca3e1c8f9c Get TARGET information from the registry on Windows 2025-01-18 16:50:45 +01:00
Martin Kroeker 7fd73a40dc Fix accidentally dropped cpu ids and add MacOS performance groups 2025-01-02 06:13:07 -08:00
Martin Kroeker be807c98a6 Identify all cores, group by performance and report the fastest TARGET 2025-01-01 21:42:10 +01:00
Martin Kroeker 1a6ecda398 utilize /proc/cpuinfo on NetBSD too 2024-12-04 15:32:26 -08:00
Martin Kroeker 50da5c2b34 Add Apple M4 as VORTEX with HAVE_SME 2024-11-12 15:20:21 -08:00
Martin Kroeker c4bb4e74fc NeoverseN2 has SVE too 2024-10-18 14:50:55 +02:00
Martin Kroeker 86720778ef write HAVE_SVE to config where applicable 2024-10-18 14:14:43 +02:00
Matthias Langer 0050a9660b Correctly detect ARM Neoverse V2 CPUs. 2024-05-16 09:59:52 +00:00
Martin Kroeker b925f61fb0 Add support for Cortex-A76 2024-04-02 19:44:17 +02:00
Martin Kroeker e1f529d024 Add OSX hw.cpufamily value for Apple M3 2023-11-12 22:37:11 +01:00
Martin Kroeker f096a339e4 Use long value fields for cpu ident on OSX 2023-04-13 18:16:09 +02:00
Martin Kroeker caa2945138 Support Apple A15/M2 cpus through the existing VORTEX target 2023-04-11 00:04:09 +02:00
Martin Kroeker 9ecfa94744 Add part numbers for A715 and X3 aliased to A710/X2 2023-02-02 17:30:30 +01:00
Martin Kroeker 09b8545fc5 Add initial support for M1 on Linux, Phytium FT2xxx series, ARM Cortex 510/710/X1/X2 2022-03-27 15:24:40 +02:00
Sunita Nadampalli 19c8f615dc OpenBLAS: aarch64: Add neoverse-v1/n2 architecture specifics 2022-01-07 00:28:17 +00:00
Martin Kroeker 22bf5c27ba Add basic support for the Fujitsu A64FX (#3415) 
* Add initial support for Fujitsu A64FX as generic ARMV8
 2021-10-18 15:00:19 +02:00
Martin Kroeker d7351deccf Fix cache reporting for Apple M1 2021-10-04 17:58:29 +02:00
Martin Kroeker 1cce778585 Fix detection of Apple M1 "Vortex" 2021-10-04 16:46:41 +02:00
Martin Kroeker f0b822a709 Update cpuid_arm64.c 2021-06-23 10:11:01 +02:00
User User-User 130327e9af OK 2021-06-22 23:58:59 +02:00
User User-User b7da75e4fd WiP CORTEX A55 support 2021-06-19 21:37:51 +02:00
Martin Kroeker 2e7ee7c716 Fix naming of L2 cache size item reported for Vortex 2020-10-18 19:22:05 +02:00
Martin Kroeker be40440ec5 Change ifdef linux to __linux for C11 compatibility 2020-09-30 22:45:18 +02:00
Martin Kroeker af5bc95503 Rename SILICON to VORTEX and fix duplicate numbering 2020-09-03 08:43:26 +02:00
Martin Kroeker 029fd01cfb Detect AppleSilicon cpu on OSX 2020-09-02 22:47:38 +02:00
Martin Kroeker 3210a42734 Report cpu as ARMV8 instead of just giving up on non-Linux hosts 2020-08-31 20:03:21 +02:00
Ashwin Sekhar T K 4e1be0e481 ARM64: Add THUNDERX3T110 Target 2020-07-26 23:32:24 -07:00
Ali Saidi c623a965f9 Add Neoverse-N1 core 
The implementation is a hybird of the ARMV8 one with some of the
improved TX2 rountines along with specifying -march=v8.2-a
 2020-02-29 03:22:04 +00:00
Martin Kroeker e8d82c01d4 Recognize Ampere EMAG8180 2020-02-19 18:49:13 +01:00
Martin Kroeker 6b83079368 Count cpu cores on ARMV8 and use that to pick the GEMM_PQ parameters (#2267) 
There is currently no simple way to query cache sizes on ARMV8, so this takes the number of cores as a trivial indication if the target is a server-class device with a big cache, or just a single-board toy or smartphone.
 2019-09-25 23:13:24 +02:00
Martin Kroeker b7bbb02447 Silence two nuisance warnings from gcc 2019-08-11 12:46:05 +02:00