1 Commits
Author SHA1 Message Date
Hugo MeilandandCursor 560caa56e6 Add Cortex-A72 DGEMM 6x8 microkernel with MR=6 packers and TRSM
TARGET=CORTEXA72 previously reused the A57 8x4 path. Add a dedicated
6x8 NEON ukernel, contiguous MR=6 panel packers (stock gemm_*copy_6 is
4+2), and UNROLL_M=6-aware TRSM kernels so HPL/dtrsm does not corrupt
the heap. DTRMM falls back to generic 2x2 until a matching kernel exists.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-08-09 10:31:35 +02:00