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103 Commits
Author SHA1 Message Date
Martin Kroeker d96daa220d Merge pull request #5290 from Srangrang/develop 
Add support for FP16 to openBLAS and shgemm on RISCV
 2025-06-24 23:10:15 +02:00
Srangrang ec14e1648c fix: resolve non-RISCV host build failed issue 
- adjust interface to disable "small matrix" pathway
- separate HFLOAT16 from BFLOAT16
- remove SHGEMM_UNROLL_M and SHGEMM_UNROLL_N equal conditions

Related to PR#5290
Co-authored-by Martin
 2025-06-15 20:25:15 +08:00
Martin Kroeker 73af02b89f use dummy2 as Inf/NAN handling flag 2025-06-12 13:33:56 -07:00
Martin Kroeker f18b7a46bf add dummy2 flag handling for inf/nan agnostic zeroing 2025-06-11 01:47:43 -07:00
guoyuanplct 2ae019161a fixed the performance problem in RISCV64_ZVL256 when OPENBLAS_K is small 2025-06-05 21:53:03 +08:00
Srangrang fb89820f20 Merge branch 'develop' of https://github.com/Srangrang/OpenBLAS into develop 2025-06-04 20:27:05 +08:00
Srangrang 4e1a381e5b fix: resolve the compilation failure without zfh instruction 
- modify the macro conditions in Makefile.system
- Delete development test code

Related to issue#5279
 2025-06-04 20:00:12 +08:00
gkdddd 670ec6f757 Added shgemm_kernel_8x8 for RISCV64_ZVL128B and shgemm_kernel_16x8 for RISCV64_ZVL256B 
Added HFLOAT16 support for RISCV64
Added shgemm_kernel_8x8 for RISCV64_ZVL128B and shgemm_kernel_16x8 for RISCV64_ZVL256B based on HFLOAT16
The instruction sets used are ZVFH and ZFH, which need to be supported by RVV1.0

Related to issue #5279
Co-authored-by Linjin Li <linjin_li@163.com>
 2025-06-03 20:14:30 +08:00
guoyuanplct d2003dc886 del lines 2025-05-29 18:38:22 +08:00
guoyuanplct 45fd2d9b07 Optimized the axpby function. 2025-05-29 17:50:44 +08:00
Srangrang 2996c25c94 add shgemm for RISCV_ZVL128B 2025-05-24 23:55:49 +08:00
guoyuanplct be9f7550b5 Format Code 2025-05-15 18:55:47 +08:00
guoyuanplct 4d213653d8 kernel/riscv64:Added support for omatcopy on riscv64. 2025-05-15 13:29:14 +08:00
guoyuanplct 9a7e3f102b kernel/riscv64:Fixed the bug of openblas_utest_ext failing in c/zgemv and some c/zgbmv tests: 2025-05-14 00:09:26 +08:00
guoyuanplct 11ffc8680e Format the code 2025-04-25 00:27:27 +08:00
guoyuanplct 7616c42095 Optimized RVV_ZVL256B Implementation of zgemv_n 
The implementation of zgemv_n using RVV_ZVL256B has been optimized.
Compared to the previous implementation, it has achieved a 1.5x
performance improvement.
 2025-04-25 00:05:15 +08:00
lglglglgy 1ff303f36e Optimizing the Implementation of GEMV on the RISC-V V Extension 
Specialized some scenarios, performed loop unrolling, and reduced the
number of multiplications.
 2025-04-08 21:18:00 +08:00
Martin Kroeker 180ba5e7d0 Merge pull request #5069 from tingboliao/dev_rotm_20250107 
Further rearranged the rotm kernel for the different architectures.
 2025-01-23 10:16:43 +01:00
tingbo.liao 3c8df6358f Further rearranged the rotm kernel for the different architectures. 
Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>
 2025-01-22 11:41:12 +08:00
tingbo.liao ef7f54b357 Optimized the gemm_tcopy_8_rvv to be compatible with the vlens 128 and 256. 
Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>
 2025-01-15 11:31:28 +08:00
tingbo.liao 0a5dbf13d3 Optimize the omatcopy_cn and zomatcopy_cn kernels with RVV 1.0 intrinsic. 
Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>
 2025-01-08 11:00:35 +08:00
tingbo.liao c37509c213 Optimize the nrm2_rvv function to further improve performance. 
Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>
 2024-12-31 08:46:55 +08:00
tingbo.liao 0bea1cfd9d Optimize the zgemm_tcopy_4_rvv function to be compatible with the situations where the vector lengths(vlens) are 128 and 256. 
Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>
 2024-12-24 10:33:27 +08:00
tingbo.liao d00cc400b1 Replaced the __riscv_vid_v_i32m2 and __riscv_vid_v_i64m2 with __riscv_vid_v_u32m2 and __riscv_vid_v_u64m2 for riscv64-unknown-linux-gnu-gcc compiling. 
Signed-off-by: tingbo.liao <tingbo.liao@starfivetech.com>
 2024-12-18 08:38:30 +08:00
Martin Kroeker a875304eb0 fix inverted conditional for NAN handling 2024-07-26 09:50:20 +02:00
Martin Kroeker f5d04318e3 Merge branch 'OpenMathLib:develop' into scalfixes 2024-07-21 13:43:43 +02:00
Martin Kroeker a815594fd1 Merge pull request #4801 from markdryan/markdryan/riscv-dynamic-arch 
Add autodetection for riscv64
 2024-07-19 17:12:07 +02:00
Martin Kroeker 2020569705 fix NAN handling and make it depend on dummy2 parameter 2024-07-17 23:55:54 +02:00
Martin Kroeker 3870995f01 make NAN handling depend on dummy2 parameter 2024-07-17 23:54:24 +02:00
Martin Kroeker 7284c533b5 make NAN handling depend on dummy2 parameter 2024-07-17 23:50:40 +02:00
Mark Ryan 67bf4b6998 Fix axpby_rvv kernels for cases where inc_y = 0 
The following openblas_utest tests fail when the RISCV64_ZVL128B is
enabled.

TEST 89/103 axpby:zaxpby_inc_0 [FAIL]
TEST 92/103 axpby:caxpby_inc_0 [FAIL]
TEST 95/103 axpby:daxpby_inc_0 [FAIL]
TEST 98/103 axpby:saxpby_inc_0 [FAIL]

The issue is that the vectorized kernels do not work when inc_y == 0.
This patch updates the kernels to fall back to the scalar algorithms
when inc_y == 0, fixing the failing tests.

Signed-off-by: Mark Ryan <markdryan@rivosinc.com>
 2024-07-15 14:24:47 +00:00
Mark Ryan 3b715e6162 Add autodetection for riscv64 
Implement DYNAMIC_ARCH support for riscv64.  Three cpu types are
supported, riscv64_generic, riscv64_zvl256b, riscv64_zvl128b.
The two non-generic kernels require CPU support for RVV 1.0 to
function correctly.  Detecting that a riscv64 device supports
RVV 1.0 is a little complicated as there are some boards on the
market that advertise support for V via hwcap but only support
RVV 0.7.1, which is not binary compatible with RVV 1.0.  The
approach taken is to first try hwprobe.  If hwprobe is not
available, we fall back to hwcap + an additional check to distinguish
between RVV 1.0 and RVV 0.7.1.

Tested on a VM with VLEN=256, a CanMV K230 with VLEN=128 (with only
the big core enabled), a Lichee Pi with RVV 0.7.1 and a VF2 with no
vector.

A compiler with RVV 1.0 support must be used to build OpenBLAS for
riscv64 when DYNAMIC_ARCH=1.

Signed-off-by: Mark Ryan <markdryan@rivosinc.com>
 2024-07-15 14:24:22 +00:00
Martin Kroeker c1019d5832 Handle INF and NAN in inputs 2024-06-27 10:58:59 +02:00
Martin Kroeker 516743f7dc fix other instances of mishandling INF 2024-05-31 16:02:12 +02:00
Martin Kroeker cf80bd8500 Update nrm2_rvv.c 2024-03-13 13:07:26 +01:00
Martin Kroeker 9baa757905 Update nrm2_vector.c 2024-03-13 11:40:14 +01:00
Martin Kroeker 18a6db6862 Update nrm2_vector.c 2024-03-13 11:10:26 +01:00
Martin Kroeker 3752e73919 handle incx < 0 2024-03-12 20:44:01 +01:00
Martin Kroeker db70c7f7fb handle incx < 0 2024-03-12 20:42:11 +01:00
Martin Kroeker dee8557d58 handle incx < 0 2024-03-12 20:40:29 +01:00
Martin Kroeker d9dff17aec handle incx < 0 2024-03-12 20:38:23 +01:00
Martin Kroeker 6b89e1f1d7 fix loop condition for incx < 0 2024-03-12 15:49:41 +01:00
Martin Kroeker 20016a0096 fix loop condition for incx < 0 2024-03-12 15:48:55 +01:00
Sergei Lewis ba17758c02 fix axpy implementations where y has a stride of 0 2024-02-16 16:00:38 +00:00
Sergei Lewis ff1523163f Fix axpy test hangs when n==0. Reenable zaxpy_vector kernel for C910V. 2024-02-09 12:59:14 +00:00
Martin Kroeker 6d8a273cca Handle zero increment(s) in C910V ?AXPBY (#4483) 
* Handle zero increment(s)
 2024-02-04 22:07:51 +01:00
Martin Kroeker 4d8dee508c temporarily disable the CAXPY/ZAXPY kernels 2024-02-04 01:05:03 +01:00
Sergei Lewis a3b0ef6596 Restore riscv64 fixes from develop branch: dot product double precision accumulation, zscal NaN handling 2024-02-01 10:32:00 +00:00
Sergei Lewis 1093def0d1 Merge branch 'risc-v' into develop 2024-01-29 11:11:39 +00:00
Martin Kroeker 889c5d026a Merge pull request #4456 from kseniyazaytseva/riscv-rvv10
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Fix BLAS and LAPACK tests for RVV 1.0 target, update to 0.12.0 intrincics
 2024-01-26 13:31:09 +01:00