Commit Graph
9676 Commits
Author SHA1 Message Date
Dayuxiaoshuiandgong-flying 7aa183bb56 Fix OMATCOPY_CT correctness issues and optimize performance
- Fixed matrix initialization to use row-major order
- Fixed memory allocation size calculation for output matrix
- Optimized RVV simulation with 4-way loop unrolling
- All test cases now pass correctness verification
- Performance improvements: up to 1.26x speedup for alpha=1.0 case

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
2025-09-11 19:29:31 +08:00
Dayuxiaoshuiandgong-flying 708d586599 Add OMATCOPY_CT performance test with RVV optimization
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
2025-09-11 19:20:26 +08:00
Dayuxiaoshuiandgong-flying 2953c7d244 Add OMATCOPY_CT performance test with RVV optimization
- Created comprehensive performance test for omatcopy_ct function
- Added RVV vectorized implementation with conditional compilation
- Included build script for SG2044 server testing
- Support both scalar and RVV optimized versions
- Added throughput measurement and detailed performance metrics

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
2025-09-11 13:29:18 +08:00
Martin Kroeker 2a95564500 Merge pull request #5442 from martin-frbg/pr5418
Make GEMM3M parameters available on 32bit X86-GENERIC
2025-09-10 15:24:12 -07:00
Martin Kroeker cb6c4392a5 Make GEMM3M parameters available on 32bit X86-GENERIC 2025-09-10 22:44:14 +02:00
Martin Kroeker a55535b01f Merge pull request #5441 from martin-frbg/fixup5431
Add message for fallback due to unavailable Zfh extension in RISCV DYNAMIC_ARCH
2025-09-10 03:42:00 -07:00
Martin Kroeker 66cc27e75f Add message for fallback due to unavailable Zfh extension 2025-09-10 10:57:02 +02:00
Martin Kroeker 5ab143736f Merge pull request #5431 from markdryan/markdryan/riscv-hf16-fix
disable fp16 flags on RISC-V unless BUILD_HFLOAT16=1
2025-09-09 14:51:47 -07:00
Martin Kroeker 2fee943edb Add CMake build support for IBM Z (#5440)
* Add ZARCH support, including DYNAMIC_ARCH
2025-09-09 22:18:51 +02:00
Martin Kroeker 90f6dd43c5 Merge pull request #5439 from martin-frbg/fixup5354
clean up duplicate assignment of cpus newer than POWER10
2025-09-08 13:10:29 -07:00
Martin Kroeker 7b1f9bedf8 clean up duplicate assignment of cpus newer than POWER10 2025-09-08 15:11:57 +02:00
Martin Kroeker e2f9f57433 Merge pull request #5432 from markdryan/markdyan/fix-rvv-detection
fix RVV 1.0 detection code
2025-09-05 13:40:23 -07:00
Martin Kroeker c31861ea62 Merge pull request #5435 from martin-frbg/update_rvv_ci
Update the riscv-collab llvm toolchain in CI to its latest nightly build
2025-09-02 14:11:16 -07:00
Martin Kroeker 57c2936a43 Merge branch 'OpenMathLib:develop' into update_rvv_ci 2025-09-02 12:09:30 -07:00
Martin Kroeker 6d070820fc Merge pull request #5436 from martin-frbg/update_osx_ci
Update Mac CI jobs as cmake is preinstalled in the runner images now
2025-09-02 12:09:09 -07:00
Martin Kroeker 1c7251ca20 remove the -llto_library option for any osx fortran compiler 2025-09-02 18:36:02 +02:00
Martin Kroeker a1331406a3 drop (re)installation of cmake on osx runners 2025-09-02 15:39:08 +02:00
Martin Kroeker c42fccccb5 Drop installation of cmake 2025-09-02 15:36:32 +02:00
Martin Kroeker 4c1a4e60a6 Update toolchain to its latest nightly build 2025-09-02 14:54:08 +02:00
Mark Ryan 7fcad02dc2 fix RVV 1.0 detection code
There were a couple of issues with the detection code used to check
for RVV 1.0 on kernels that do not support hwprobe.

1. The vtype clobber was missing
2. The wrong form of vsetvli was being used. The vsetvli x0, x0 form
   is inappropriate for this use case as it can only be safely used
   in code where the value of vtype is known.  The use of vsetvli
   x0, x0 here can lead to a failure to detect RVV 1.0, if,
   for example, the vill bit happens to be set before
   detect_riscv64_rvv100 is called.

We fix both issues by adding the missing clobber and replacing the
first parameter to vsetvli with t0 (which we add to our clobbers).
2025-08-28 14:20:37 +00:00
Mark Ryan ce79fe12fd disable fp16 flags on RISC-V unless BUILD_HFLOAT16=1
The compiler options that enable 16 bit floating point instructions
should not be enabled by default when building the RISCV64_ZVL128B
and RISCV64_ZVL256B targets.  The zfh and zvfh extensions are not part
of the 'V' extension and are not required by any of the RVA profiles.
There's no guarantee that kernels built with zfh and zvfh will work
correctly on fully compliant RVA23U64 devices.

To fix the issue we only build the RISCV64_ZVL128B and RISCV64_ZVL256B
kernels with the half float flags if BUILD_HFLOAT16=1.  We also update
the RISC-V dynamic detection code to disable the RISCV64_ZVL128B and
RISCV64_ZVL256B kernels at runtime if we've built with DYNAMIC_ARCH=1
and BUILD_HFLOAT16=1 and are running on a device that does not support
both Zfh and Zvfh.

Fixes: https://github.com/OpenMathLib/OpenBLAS/issues/5428
2025-08-28 09:41:07 +00:00
Martin Kroeker 06c09deee9 Merge pull request #5426 from hideaki-motoki/issue5417_axpy_sve
Implementing SVE in `[SD]AXPY` Kernels for `A64FX` and `Graviton3E`
2025-08-26 01:10:14 -07:00
Martin Kroeker da7d0f4a38 Merge pull request #5427 from yuanjia111/develop
Optimize the gemv_t_vector.c  kernel  for  RISCV64_ZVL256B target
2025-08-25 06:45:44 -07:00
Martin Kroeker 2b5d8c789d remove debugging printout 2025-08-24 13:50:08 -07:00
Martin Kroeker 1b88c9c742 remove debugging printouts 2025-08-24 13:48:22 -07:00
Martin Kroeker b4fc09e9e1 Add registers d8 to d15 to clobber lists as the code does not expressly save them 2025-08-23 14:39:27 -07:00
Martin Kroeker 8e50b8d525 Add d8 to d15 to clobber lists as the code does not expressly save them 2025-08-23 14:36:49 -07:00
Martin Kroeker 7f89c6f353 smh-based direct sgemm currently requires leading dimensions to be same as matrix dimension 2025-08-23 14:20:15 -07:00
yuanjia c2cc7a3602 riscv64: optimize gemv_t_vector.c 2025-08-22 16:14:14 +08:00
h-motoki e23f9c6642 Merge remote-tracking branch 'upstream/develop' into issue5417_axpy_sve 2025-08-21 22:16:28 +09:00
Martin Kroeker b3f247ae5a Merge pull request #5425 from martin-frbg/fixup5389
Increase L2 defaults for RISCV X280 / ZVL256B and ARM SVE targets in CMake cross-compilation
2025-08-21 05:13:34 -07:00
h-motoki 855945befb Implementing SVE in [SD]AXPY Kernels for A64FX and Graviton3E 2025-08-21 20:56:58 +09:00
Martin Kroeker 7c1839899e Increase assumed L2 sizes for RISCV X280 / ZVL256B and for SVE-capable ARM64 2025-08-21 11:57:07 +02:00
Martin Kroeker 1ee8879c78 Add VORTEXM4 2025-08-20 09:59:32 -07:00
Martin Kroeker edaa73fd24 Hide the local 2VLx2VL symbol as static is insufficient for this with gcc 2025-08-20 06:33:28 -07:00
Martin Kroeker 501728a354 adjust register 20 accesses to 21 after moving x18 2025-08-20 06:24:38 -07:00
Martin Kroeker 107c883c8a Update SME-related kernels 2025-08-19 05:13:28 -07:00
Martin Kroeker 05dbb54362 Delete misplaced file 2025-08-19 05:12:09 -07:00
Martin Kroeker 4609732e69 Relax version number requirement for AppleClang 2025-08-18 14:54:20 -07:00
Martin Kroeker bf98e448eb Add VORTEXM4 to DYNAMIC_ARCH list 2025-08-18 14:43:08 -07:00
Martin Kroeker 0bc19a1335 Update SME kernel details 2025-08-18 14:38:16 -07:00
Martin Kroeker 426b5f23ed Add compiler options for VORTEXM4 2025-08-18 14:35:36 -07:00
Martin Kroeker 4328c91e27 relax requirements in compiler SME capability check 2025-08-18 14:34:51 -07:00
Martin Kroeker c794d0a4ce Add VORTEXM4 2025-08-18 14:33:24 -07:00
Martin Kroeker a4f5fec46e Add compiler options for VORTEXM4 2025-08-18 14:32:07 -07:00
Martin Kroeker ca542f319f Add VORTEXM4 2025-08-18 08:41:38 -07:00
Martin Kroeker 18f9582f3e Add VORTEXM4 2025-08-18 01:54:09 -07:00
Martin Kroeker 4e2a8c18e5 Split VORTEXM4 from VORTEX target due to SME support 2025-08-18 01:53:04 -07:00
Martin Kroeker 30970460b8 Add VORTEXM4 target 2025-08-18 01:52:05 -07:00
Martin Kroeker b0a00fbd62 Add minimal compiler flags for VORTEXM4 2025-08-18 01:51:10 -07:00