Chip Kerchner
eb9bbcc299
Common unroll code.
2026-03-14 16:38:12 +00:00
Chip Kerchner
fda433f25a
Unroll K for N less than or equal to 4.
2026-03-13 22:17:47 +00:00
Chip Kerchner
9c16449dfd
Add K-unrolling to M = 8. Other small changes.
2026-03-13 15:59:29 +00:00
Chip Kerchner
6d6af1dee5
Add bool types for C.
2026-03-12 13:13:34 +00:00
Chip Kerchner
376d3a138f
Fast performing edges for FP32 GEMM of RVV.
2026-03-12 12:33:25 +00:00
Chip Kerchner
efe63e7970
Add pre-RVA23 to BF16 GEMM.
2026-02-15 15:49:59 +00:00
Chip Kerchner
1d6aa0dc31
Add dummy memsets - just in case.
2026-02-13 20:03:35 +00:00
Chip Kerchner
7a1d23400f
Add flag for not converting A & B - will be used in future to do conversion during packing.
2026-02-13 19:00:41 +00:00
Chip Kerchner
1cc377ef61
Only convert B if M is greater or equal to 4.
2026-02-13 18:14:11 +00:00
Chip Kerchner
0acb60aab3
Conversion from BF16 to FP32 only once.
2026-02-13 17:55:15 +00:00
Chip Kerchner
9701a80a9f
One small change.
2026-02-12 20:35:41 +00:00
Chip Kerchner
4121a22c02
Convert BF16 values once (and vectorized).
2026-02-12 18:45:39 +00:00
Chip Kerchner
33560437f5
Convert inputs from BF16 to FP32 and use FP32 vector madds. 18% faster.
2026-02-11 19:50:48 +00:00
Chip Kerchner
e3cb067bf4
Fixed MADD to use float16 values. Use LMUL = 2 in main loop. Now 1.85X faster on BananaPi.
2026-02-11 00:27:27 +00:00
Chip Kerchner
74d9fe2832
Forget to add defintion.
2026-02-10 19:00:26 +00:00
Chip Kerchner
aa1cebd45b
128-bit versions.
2026-02-10 18:30:02 +00:00
Chip Kerchner
b5f2a50fe9
Added ability to accumulate in FP16 for GEMM. Widens once at the end of loops.
2026-02-10 17:30:05 +00:00
daichengrong
98a8230dee
Optimize ZROT_RVV for the unit-stride case (inc_x = inc_y = 1)
2025-11-18 17:34:27 +08:00
Chip Kerchner
00a7336fc9
Missing one gemv conversion.
2025-11-04 22:27:53 +00:00
Chip Kerchner
edf2e5900c
Prevent possible conversion from bfloat16 to __bf16.
2025-11-04 21:00:37 +00:00
Chip Kerchner
03a83778bb
Tie in SHGEMV for RISC-V.
2025-10-08 14:08:29 +00:00
Chip Kerchner
f552040c5d
Fix stride issue.
2025-10-07 17:17:18 +00:00
Chip Kerchner
aecb7f9537
Change signature of SBGEMV.
2025-10-07 13:14:20 +00:00
Chip Kerchner
809e1cba8f
Better FP16 vectorized GEMV - 20% faster.
2025-10-06 13:19:03 +00:00
Chip Kerchner
e07a9ae418
Merge branch 'develop' into vectorSBGEMV
2025-10-03 17:13:29 +00:00
Chip Kerchner
588f0e87cc
Add SBGEMV and SHGEMV routines to RISC-V.
2025-10-03 17:09:16 +00:00
Chip Kerchner
36f9cb85b1
Fix pre-RVV 1.0.
2025-09-30 22:41:31 +00:00
Chip Kerchner
2d82d144e2
Tranverse matrix data in a cache friendly manner for GEMV_N (RISCV).
2025-09-30 21:22:10 +00:00
Chip Kerchner
07d0e742c2
Add vectorized packing for FP16 and BF16. Reactivate vector packing for FP64 transposed.
2025-09-26 14:50:38 +00:00
Chip Kerchner
92f09a6a98
Add BF16 sbgemm on RISCV.
2025-09-22 14:32:43 +00:00
Chip Kerchner
a4abf7828e
Fix _Float16 casting issue and reduce LMUL for certain vector instruction from m2 to m1.
2025-09-18 21:30:22 +00:00
学习中的牛马
8b7e4c2b5c
Merge branch 'OpenMathLib:develop' into develop
2025-09-15 12:08:17 +08:00
Dayuxiaoshui
2265318d3e
Optimize RISC-V RVV omatcopy implementation with latest RVV API\n\nCo-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
2025-09-15 11:46:50 +08:00
yuanjia
826cb4588f
remove unused variable
2025-09-13 11:35:49 +08:00
yuanjia
53d7452cdf
riscv: gemv_t_vector.c optimize
2025-09-13 11:24:49 +08:00
Dayuxiaoshui and gong-flying
bd45b82ed0
Optimize RISC-V RVV omatcopy_ct implementation with advanced vectorization
...
- Implement block-based memory access optimization (64x64 blocks)
- Add 4-way loop unrolling to reduce loop overhead
- Optimize VSETVL calls to improve vectorization efficiency
- Add software prefetching for better memory access patterns
- Implement fast path for small matrices (<64x64)
- Add cross-compilation script for RISC-V testing
- Improve boundary handling with separate main/tail loops
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn >
2025-09-11 20:01:39 +08:00
Dayuxiaoshui and gong-flying
708d586599
Add OMATCOPY_CT performance test with RVV optimization
...
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn >
2025-09-11 19:20:26 +08:00
yuanjia
c2cc7a3602
riscv64: optimize gemv_t_vector.c
2025-08-22 16:14:14 +08:00
Martin Kroeker
9d6df1dd3e
Merge pull request #5422 from ChipKerchner/addRVVVectorizedPacking
...
Add and use vectorized packing in ZVL128B and ZVL256B for RISCV
2025-08-16 13:45:35 -07:00
Chip Kerchner
64401b4417
Disable vectorized packing for DGEMM - since it is slower than scalar.
2025-08-13 13:41:12 +00:00
Chip Kerchner
c00afc86a6
Add and use vectorized packing to ZVL128B and ZVL256B. Up to 3x+ faster than generic scalar functions.
2025-08-12 17:18:56 +00:00
Chip Kerchner
72f082f31d
Fix bad vector zero initializer and other compiler warnings for RISC-V.
2025-07-30 14:04:43 +00:00
Martin Kroeker
e2d941e9af
Declare the "small" kernel static in addition to inline
2025-07-22 11:02:32 +02:00
Martin Kroeker
8214700930
Declare the "small" kernel static in addition to inline
2025-07-22 11:01:37 +02:00
Martin Kroeker
d96daa220d
Merge pull request #5290 from Srangrang/develop
...
Add support for FP16 to openBLAS and shgemm on RISCV
2025-06-24 23:10:15 +02:00
Srangrang
ec14e1648c
fix: resolve non-RISCV host build failed issue
...
- adjust interface to disable "small matrix" pathway
- separate HFLOAT16 from BFLOAT16
- remove SHGEMM_UNROLL_M and SHGEMM_UNROLL_N equal conditions
Related to PR#5290
Co-authored-by Martin
2025-06-15 20:25:15 +08:00
Martin Kroeker
73af02b89f
use dummy2 as Inf/NAN handling flag
2025-06-12 13:33:56 -07:00
Martin Kroeker
f18b7a46bf
add dummy2 flag handling for inf/nan agnostic zeroing
2025-06-11 01:47:43 -07:00
guoyuanplct
2ae019161a
fixed the performance problem in RISCV64_ZVL256 when OPENBLAS_K is small
2025-06-05 21:53:03 +08:00
Srangrang
fb89820f20
Merge branch 'develop' of https://github.com/Srangrang/OpenBLAS into develop
2025-06-04 20:27:05 +08:00
Chip Kerchner