Chip Kerchner
6a23c36313
Unroll inner loop - 2 rows at a time. Up to 1.5X faster.
2026-06-02 16:39:16 +00:00
Chip Kerchner
f3f718b228
Fix contiguous memory check for SGEMM and DGEMM.
2026-05-18 18:56:29 +00:00
Chip Kerchner
0a4d6b2e11
Forgot files from previous check-in.
2026-04-02 20:15:32 +00:00
Chip Kerchner
cc1b5794a0
Reduce number of vectors in use from 32 to 24 for last stage of main block - now full LMUL2.
2026-04-02 20:14:57 +00:00
Chip Kerchner
22b7950baa
Use LMUL2 for calculations in main block - just break them apart before last stage.
2026-04-02 16:24:15 +00:00
Chip Kerchner
3b1aef12c7
Use LMUL2 loads in main block.
2026-04-02 13:20:16 +00:00
Chip Kerchner
daa3215fb4
Remove shadow variable.
2026-03-31 14:41:38 +00:00
Chip Kerchner
d69be17b6f
Convert 2X LMUL1 instructions to 1X LMUL2. Improved FP64 GEMM edges - up to more than 3X faster.
2026-03-30 18:50:27 +00:00
Chip Kerchner
8fc0004024
Fix another typo.
2026-03-24 13:04:54 +00:00
Chip Kerchner
ebf4cd1c6e
Fix typo.
2026-03-22 18:28:21 +00:00
Chip Kerchner
1bb72b223d
Only initialize unused variables to prevent GCC warnings.
2026-03-20 16:00:33 +00:00
Chip Kerchner
a8a00bbf4f
Avoid greater than 4 segment load and store penalties by using 2. Fix mf2 length.
2026-03-19 21:17:20 +00:00
Chip Kerchner
1e48686df8
Merge remote-tracking branch 'origin/develop' into fasterRVVEdges
2026-03-19 12:15:19 +00:00
Chip Kerchner
d832ee5086
More global optimzation and clean up.
2026-03-18 13:43:03 +00:00
Chip Kerchner
477dd40f07
Simplier loops.
2026-03-17 21:18:30 +00:00
Chip Kerchner
79d9fe39c2
Use mf2 instead of m1.
2026-03-17 16:06:54 +00:00
Chip Kerchner
f927b9448a
Global optimizations.
2026-03-16 21:32:17 +00:00
Chip Kerchner
010f24f961
Better K.
2026-03-16 13:22:31 +00:00
daichengrong
aa967ef6ba
Optimize ZROT_RVV for the non-unit-stride case
...
Optimize the RVV implementation of ZROT when inc_x and inc_y are
non-unit strides (inc_x != 1, inc_y != 1).
Reorder several operations to reduce vector register pressure and
avoid unnecessary vector register spill to the stack. This helps GCC
keep vector values in registers and reduces redundant spill/reload
instructions, improving runtime performance.
No functional change.
Signed-off-by: daichengrong <daichengrong@iscas.ac.cn >
2026-03-16 14:22:54 +08:00
Chip Kerchner
b0ee407943
Preserve K.
2026-03-14 17:46:42 +00:00
Chip Kerchner
eb9bbcc299
Common unroll code.
2026-03-14 16:38:12 +00:00
Chip Kerchner
fda433f25a
Unroll K for N less than or equal to 4.
2026-03-13 22:17:47 +00:00
Chip Kerchner
9c16449dfd
Add K-unrolling to M = 8. Other small changes.
2026-03-13 15:59:29 +00:00
Chip Kerchner
6d6af1dee5
Add bool types for C.
2026-03-12 13:13:34 +00:00
Chip Kerchner
376d3a138f
Fast performing edges for FP32 GEMM of RVV.
2026-03-12 12:33:25 +00:00
Chip Kerchner
efe63e7970
Add pre-RVA23 to BF16 GEMM.
2026-02-15 15:49:59 +00:00
Chip Kerchner
1d6aa0dc31
Add dummy memsets - just in case.
2026-02-13 20:03:35 +00:00
Chip Kerchner
7a1d23400f
Add flag for not converting A & B - will be used in future to do conversion during packing.
2026-02-13 19:00:41 +00:00
Chip Kerchner
1cc377ef61
Only convert B if M is greater or equal to 4.
2026-02-13 18:14:11 +00:00
Chip Kerchner
0acb60aab3
Conversion from BF16 to FP32 only once.
2026-02-13 17:55:15 +00:00
Chip Kerchner
9701a80a9f
One small change.
2026-02-12 20:35:41 +00:00
Chip Kerchner
4121a22c02
Convert BF16 values once (and vectorized).
2026-02-12 18:45:39 +00:00
Chip Kerchner
33560437f5
Convert inputs from BF16 to FP32 and use FP32 vector madds. 18% faster.
2026-02-11 19:50:48 +00:00
Chip Kerchner
e3cb067bf4
Fixed MADD to use float16 values. Use LMUL = 2 in main loop. Now 1.85X faster on BananaPi.
2026-02-11 00:27:27 +00:00
Chip Kerchner
74d9fe2832
Forget to add defintion.
2026-02-10 19:00:26 +00:00
Chip Kerchner
aa1cebd45b
128-bit versions.
2026-02-10 18:30:02 +00:00
Chip Kerchner
b5f2a50fe9
Added ability to accumulate in FP16 for GEMM. Widens once at the end of loops.
2026-02-10 17:30:05 +00:00
daichengrong
98a8230dee
Optimize ZROT_RVV for the unit-stride case (inc_x = inc_y = 1)
2025-11-18 17:34:27 +08:00
Chip Kerchner
00a7336fc9
Missing one gemv conversion.
2025-11-04 22:27:53 +00:00
Chip Kerchner
edf2e5900c
Prevent possible conversion from bfloat16 to __bf16.
2025-11-04 21:00:37 +00:00
Chip Kerchner
03a83778bb
Tie in SHGEMV for RISC-V.
2025-10-08 14:08:29 +00:00
Chip Kerchner
f552040c5d
Fix stride issue.
2025-10-07 17:17:18 +00:00
Chip Kerchner
aecb7f9537
Change signature of SBGEMV.
2025-10-07 13:14:20 +00:00
Chip Kerchner
809e1cba8f
Better FP16 vectorized GEMV - 20% faster.
2025-10-06 13:19:03 +00:00
Chip Kerchner
e07a9ae418
Merge branch 'develop' into vectorSBGEMV
2025-10-03 17:13:29 +00:00
Chip Kerchner
588f0e87cc
Add SBGEMV and SHGEMV routines to RISC-V.
2025-10-03 17:09:16 +00:00
Chip Kerchner
36f9cb85b1
Fix pre-RVV 1.0.
2025-09-30 22:41:31 +00:00
Chip Kerchner
2d82d144e2
Tranverse matrix data in a cache friendly manner for GEMV_N (RISCV).
2025-09-30 21:22:10 +00:00
Chip Kerchner
07d0e742c2
Add vectorized packing for FP16 and BF16. Reactivate vector packing for FP64 transposed.
2025-09-26 14:50:38 +00:00
Chip Kerchner
92f09a6a98
Add BF16 sbgemm on RISCV.
2025-09-22 14:32:43 +00:00
Chip Kerchner