hmeiland
b8949d1663
The StarFive JH7110's U74 cores implement rv64imafdc_..._zba_zbb, so the U74 target now compiles with -march=rv64imafdc_zba_zbb. The generic RISCV64_GENERIC target stays at bare rv64imafdc for portability across unknown RV64GC cores. Measured on the VisionFive 2 (GCC 13.3, -mtune=sifive-u74 held constant): GCC emits Zba shift-add instructions in the packing routines, but DGEMM is unchanged -- the 4x4 kernel holds 1.533 GF either way and packing 1.74 vs 1.75 GB/s. The 4x4 micro-kernel is FMA-bound (fused fmadd.d with immediate-offset loads) and packing is LPDDR4-bandwidth-bound, so integer address generation is not on the critical path. The flag is nonetheless the correct -march for the silicon, is free, and can only help address-gen-bound code elsewhere in the library. The remaining GEMM headroom on the U74 is microarchitectural scheduling (a hand-written assembly micro-kernel), not the ISA.
118 lines
2.7 KiB
Makefile
118 lines
2.7 KiB
Makefile
# This is triggered by Makefile.system and runs before any of the code is built.
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export BINARY
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export USE_OPENMP
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ifdef DYNAMIC_ARCH
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override HOST_CFLAGS += -DDYNAMIC_ARCH
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endif
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ifdef TARGET_CORE
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TARGET_MAKE = Makefile_kernel.conf
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TARGET_CONF = config_kernel.h
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else
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TARGET_MAKE = Makefile.conf
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TARGET_CONF = config.h
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endif
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ifdef USE_PERL
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SCRIPTSUFFIX = .pl
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else
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SCRIPTSUFFIX =
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endif
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# CPUIDEMU = ../../cpuid/table.o
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ifdef CPUIDEMU
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EXFLAGS = -DCPUIDEMU -DVENDOR=99
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endif
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ifeq ($(TARGET), MIPS24K)
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TARGET_FLAGS = -mips32r2
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endif
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ifeq ($(TARGET), MIPS1004K)
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TARGET_FLAGS = -mips32r2
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endif
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ifeq ($(TARGET), P5600)
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TARGET_FLAGS = -mips32r5
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endif
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ifeq ($(TARGET), I6400)
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TARGET_FLAGS = -mips64r6
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endif
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ifeq ($(TARGET), P6600)
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TARGET_FLAGS = -mips64r6
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endif
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ifeq ($(TARGET), I6500)
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TARGET_FLAGS = -mips64r6
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endif
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ifeq ($(TARGET), C910V)
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TARGET_FLAGS = -march=rv64gcv0p7_zfh_xtheadc -mabi=lp64d
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endif
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ifeq ($(TARGET), CK860FV)
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TARGET_FLAGS = -march=ck860v -mcpu=ck860fv -mfdivdu -mhard-float
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endif
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ifeq ($(TARGET), x280)
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TARGET_FLAGS = -march=rv64imafdcv_zba_zbb_zfh -mabi=lp64d
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endif
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ifeq ($(TARGET), RISCV64_ZVL256B)
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TARGET_FLAGS = -march=rv64imafdcv -mabi=lp64d
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endif
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ifeq ($(TARGET), RISCV64_ZVL128B)
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TARGET_FLAGS = -march=rv64imafdcv -mabi=lp64d
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endif
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ifeq ($(TARGET), RISCV64_GENERIC)
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TARGET_FLAGS = -march=rv64imafdc -mabi=lp64d
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endif
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ifeq ($(TARGET), U74)
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TARGET_FLAGS = -march=rv64imafdc_zba_zbb -mabi=lp64d
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endif
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all: getarch_2nd
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./getarch_2nd 0 >> $(TARGET_MAKE)
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./getarch_2nd 1 >> $(TARGET_CONF)
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$(TARGET_CONF): c_check$(SCRIPTSUFFIX) f_check$(SCRIPTSUFFIX) getarch
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./c_check$(SCRIPTSUFFIX) $(TARGET_MAKE) $(TARGET_CONF) "$(CC)" $(TARGET_FLAGS) $(CFLAGS)
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ifneq ($(ONLY_CBLAS), 1)
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./f_check$(SCRIPTSUFFIX) $(TARGET_MAKE) $(TARGET_CONF) "$(FC)" $(TARGET_FLAGS)
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else
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#When we only build CBLAS, we set NOFORTRAN=2
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echo "NOFORTRAN=2" >> $(TARGET_MAKE)
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echo "NO_FBLAS=1" >> $(TARGET_MAKE)
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echo "F_COMPILER=GFORTRAN" >> $(TARGET_MAKE)
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echo "BU=_" >> $(TARGET_MAKE)
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echo "#define BUNDERSCORE _" >> $(TARGET_CONF)
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echo "#define NEEDBUNDERSCORE 1" >> $(TARGET_CONF)
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endif
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./getarch 0 >> $(TARGET_MAKE)
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./getarch 1 >> $(TARGET_CONF)
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getarch : getarch.c cpuid.S dummy $(CPUIDEMU)
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avx512=$$(./c_check$(SCRIPTSUFFIX) - - "$(CC)" $(TARGET_FLAGS) $(CFLAGS) | grep NO_AVX512); \
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rv64gv=$$(./c_check$(SCRIPTSUFFIX) - - "$(CC)" $(TARGET_FLAGS) $(CFLAGS) | grep NO_RV64GV); \
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$(HOSTCC) $(HOST_CFLAGS) $(EXFLAGS) $${avx512:+-D$${avx512}} $${rv64gv:+-D$${rv64gv}} -o $(@F) getarch.c cpuid.S $(CPUIDEMU)
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getarch_2nd : getarch_2nd.c $(TARGET_CONF) dummy
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ifndef TARGET_CORE
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$(HOSTCC) -I. $(HOST_CFLAGS) -o $(@F) getarch_2nd.c
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else
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$(HOSTCC) -I. $(HOST_CFLAGS) -DBUILD_KERNEL -o $(@F) getarch_2nd.c
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endif
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dummy:
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.PHONY: dummy
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