hmeiland
a3620c264a
The SiFive U74 (RV64GC; e.g. StarFive JH7110 / VisionFive 2) is a scalar,
in-order core with no RVV, so today it falls back to RISCV64_GENERIC whose
S/D GEMM uses the generic 2x2 C micro-kernel.
Per the U74 Core Complex Manual (Table 169) fmadd.d has a 7-cycle latency
at repeat rate 1 (fully pipelined). A 2x2 tile exposes only 4 independent
accumulator chains -- fewer than the FMA latency -- so the FP pipe stalls
on the accumulator dependency, and the 1:1 load:FMA ratio saturates the
single load/store pipe ("only one outstanding line fill", manual 8.2).
This adds a portable 4x4 GEMM micro-kernel and a dedicated U74 target:
- kernel/generic/gemmkernel_4x4.c: 16-accumulator 4x4 register tile. 16
independent chains exceed the 7-cycle latency, and the load:FMA ratio
drops to 1:2. 16 acc + 4 A + 4 B fit RV64G's 32 FP registers without
spilling. Full 4/2/1 edge handling in both M and N.
- U74 target wiring: getarch.c (FORCE_U74, 32 KiB/64 B L1D, 2 MiB L2),
param.h (S/D UNROLL 4/4; complex stays 2/2), kernel/riscv64/KERNEL.U74
(S/D GEMM -> gemmkernel_4x4 + gemm_[nt]copy_4; S/D TRMM -> existing
trmmkernel_4x4), Makefile.prebuild + Makefile.riscv64 (-mtune=sifive-u74),
TargetList.txt, cpuid_riscv64.c.
The 4x4 kernel was verified numerically against a naive reference GEMM,
driven through the real gemm_tcopy_4 / gemm_ncopy_4 packing routines,
across 27,436 M/N/K x alpha combinations covering every 4/2/1 tail case:
worst absolute error 0.
Build with: make TARGET=U74
161 lines
1.7 KiB
Plaintext
161 lines
1.7 KiB
Plaintext
Force Target Examples:
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make TARGET=NEHALEM
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make TARGET=LOONGSON3A BINARY=64
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make TARGET=ISTANBUL
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Supported List:
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1.X86/X86_64
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a)Intel CPU:
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P2
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KATMAI
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COPPERMINE
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NORTHWOOD
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PRESCOTT
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BANIAS
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YONAH
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CORE2
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PENRYN
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DUNNINGTON
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NEHALEM
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SANDYBRIDGE
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HASWELL
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SKYLAKEX
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ATOM
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COOPERLAKE
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SAPPHIRERAPIDS
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b)AMD CPU:
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ATHLON
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OPTERON
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OPTERON_SSE3
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BARCELONA
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SHANGHAI
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ISTANBUL
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BOBCAT
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BULLDOZER
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PILEDRIVER
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STEAMROLLER
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EXCAVATOR
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ZEN
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c)VIA CPU:
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SSE_GENERIC
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VIAC3
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NANO
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2.Power CPU:
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POWER4
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POWER5
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POWER6
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POWER7
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POWER8
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POWER9
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POWER10
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POWER11
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PPCG4
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PPC970
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PPC970MP
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PPC440
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PPC440FP2
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CELL
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3.MIPS CPU:
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P5600
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MIPS1004K
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MIPS24K
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4.MIPS64 CPU:
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MIPS64_GENERIC
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SICORTEX
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LOONGSON3A
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LOONGSON3B
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I6400
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P6600
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I6500
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5.IA64 CPU:
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ITANIUM2
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6.SPARC CPU:
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SPARC
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SPARCV7
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7.ARM CPU:
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CORTEXA15
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CORTEXA9
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ARMV7
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ARMV6
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ARMV5
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8.ARM 64-bit CPU:
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ARMV8
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CORTEXA53
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CORTEXA57
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CORTEXA72
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CORTEXA73
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CORTEXA76
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CORTEXA510
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CORTEXA710
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CORTEXX1
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CORTEXX2
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NEOVERSEN1
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NEOVERSEV1
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NEOVERSEN2
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NEOVERSEV2
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CORTEXA55
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EMAG8180
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FALKOR
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THUNDERX
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THUNDERX2T99
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TSV110
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THUNDERX3T110
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VORTEX
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VORTEXM4
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A64FX
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ARMV8SVE
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ARMV9SME
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FT2000
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9.System Z:
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ZARCH_GENERIC
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Z13
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Z14
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10.RISC-V 64:
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RISCV64_GENERIC (e.g. PolarFire Soc/SiFive U54)
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RISCV64_ZVL128B
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C910V
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x280
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RISCV64_ZVL256B
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U74 (e.g. SiFive U74 / StarFive JH7110 / VisionFive 2)
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11.LOONGARCH64:
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// LOONGSONGENERIC/LOONGSON2K1000/LOONGSON3R5 are legacy names,
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// and it is recommended to use the more standardized naming conventions
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// LA64_GENERIC/LA264/LA464. You can still specify TARGET as
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// LOONGSONGENERIC/LOONGSON2K1000/LOONGSON3R5 during compilation or runtime,
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// and they will be internally relocated to LA64_GENERIC/LA264/LA464.
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LOONGSONGENERIC
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LOONGSON2K1000
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LOONGSON3R5
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LA64_GENERIC
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LA264
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LA464
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12. Elbrus E2000:
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E2K
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13. Alpha
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EV4
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EV5
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EV6
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14.CSKY
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CSKY
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CK860FV
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15. WebAssembly/Emscripten:
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WASM128_GENERIC
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