499 lines
18 KiB
ArmAsm
499 lines
18 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2026, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#include "loongarch64_asm.S"
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#define M $a0
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#define N $a1
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#define K $a2
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#define A $a3
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#define LDA $a4
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#define ALPHA $f0
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#define B $a5
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#define LDB $a6
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#define C $a7
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#define LDC $t0
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#ifdef B0
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#define BETA $f1
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#endif
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#undef ZERO
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#define ZERO $r0
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#define M32 $t1
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#define M16 $t1
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#define M8 $t1
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#define M4 $t1
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#define M2 $t1
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#define M1 $t1
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#define N4 $t2
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#define N2 $t2
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#define N1 $t2
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#define K4 $t3
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#define A0 $t4
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#define X0 $t5
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#define B_cur $t6
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#define C0 $s0
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#define C1 $s1
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#define C2 $s2
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#define C3 $s3
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#define K1 $s4
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#define VALPHA $xr0
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#ifndef B0
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#define VBETA $xr1
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#endif
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#define D0 $xr2
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#define D1 $xr3
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#define D2 $xr4
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#define D3 $xr5
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#define D4 $xr6
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#define D5 $xr7
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#define D6 $xr8
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#define D7 $xr9
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#define D8 $xr10
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#define D9 $xr11
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#define D10 $xr12
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#define D11 $xr13
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#define D12 $xr14
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#define D13 $xr15
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#define D14 $xr16
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#define D15 $xr17
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#define S0 $xr18
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#define S1 $xr19
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#define S2 $xr20
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#define S3 $xr21
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#define Z0 $xr22
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#define Z1 $xr23
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#define Z2 $xr24
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#define Z3 $xr25
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#define V0 $vr2
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#define V1 $vr3
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#define V2 $vr4
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#define V3 $vr5
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#define F0 $f2
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#define F1 $f3
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#define F2 $f4
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#define F3 $f5
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.macro SGEMM_SMALL_KERNEL_NT_TAIL M
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PTR_SRAI N4, N, 2
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move A0, A
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move B_cur, B
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move C0, C
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PTR_ADD C1, C0, LDC
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PTR_ADD C2, C1, LDC
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PTR_ADD C3, C2, LDC
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beqz N4, .L_M\M\()_N3
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.L_M\M\()_N4:
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GXOR xv, v, D0, D0, D0, D1, D1, D1, D2, D2, D2, D3, D3, D3
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move K1, K
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move X0, B_cur
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PTR_ADDI N4, N4, -1
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bge ZERO, K, .L_M\M\()_N4_END
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.L_M\M\()_N4_K1:
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PTR_ADDI K1, K1, -1
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GLD xv, , S0, A0, 0x00
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GLDREPL xv, w, Z0, X0, 0x00, Z1, X0, 0x04, Z2, X0, 0x08, Z3, X0, 0x0C
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GMADD xvf, s, D0, S0, Z0, D0, D1, S0, Z1, D1, D2, S0, Z2, D2, D3, S0, Z3, D3
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PTR_ADD X0, X0, LDB
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PTR_ADD A0, A0, LDA
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bnez K1, .L_M\M\()_N4_K1
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.L_M\M\()_N4_END:
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GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA, D2, D2, VALPHA, D3, D3, VALPHA
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#ifndef B0
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GLD xv, , S0, C0, 0x00
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GMADD xvf, s, D0, S0, VBETA, D0
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GLD xv, , S0, C1, 0x00
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GMADD xvf, s, D1, S0, VBETA, D1
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GLD xv, , S0, C2, 0x00
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GMADD xvf, s, D2, S0, VBETA, D2
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GLD xv, , S0, C3, 0x00
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GMADD xvf, s, D3, S0, VBETA, D3
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#endif
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.if \M == 8
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GST xv, , D0, C0, 0x00, D1, C1, 0x00, D2, C2, 0x00, D3, C3, 0x00
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.elseif \M == 4
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GST v, , V0, C0, 0x00, V1, C1, 0x00, V2, C2, 0x00, V3, C3, 0x00
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.elseif \M == 2
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GST f, d, F0, C0, 0x00, F1, C1, 0x00, F2, C2, 0x00, F3, C3, 0x00
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.elseif \M == 1
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GST f, s, F0, C0, 0x00, F1, C1, 0x00, F2, C2, 0x00, F3, C3, 0x00
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.endif
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PTR_ALSL C0, LDC, C0, 2
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PTR_ALSL C1, LDC, C1, 2
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PTR_ALSL C2, LDC, C2, 2
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PTR_ALSL C3, LDC, C3, 2
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// Update B_cur to advance N by 4 (16 bytes)
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PTR_ADDI B_cur, B_cur, 16
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move A0, A
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bnez N4, .L_M\M\()_N4
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.L_M\M\()_N3:
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andi N2, N, 0x02
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beqz N2, .L_M\M\()_N1
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.L_M\M\()_N2:
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GXOR xv, v, D0, D0, D0, D1, D1, D1
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move K1, K
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move X0, B_cur
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bge ZERO, K, .L_M\M\()_N2_END
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.L_M\M\()_N2_K1:
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PTR_ADDI K1, K1, -1
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GLD xv, , S0, A0, 0x00
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GLDREPL xv, w, Z0, X0, 0x00, Z1, X0, 0x04
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GMADD xvf, s, D0, S0, Z0, D0, D1, S0, Z1, D1
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PTR_ADD X0, X0, LDB
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PTR_ADD A0, A0, LDA
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bnez K1, .L_M\M\()_N2_K1
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.L_M\M\()_N2_END:
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GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA
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#ifndef B0
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GLD xv, , S0, C0, 0x00
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GMADD xvf, s, D0, S0, VBETA, D0
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GLD xv, , S0, C1, 0x00
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GMADD xvf, s, D1, S0, VBETA, D1
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#endif
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.if \M == 8
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GST xv, , D0, C0, 0x00, D1, C1, 0x00
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.elseif \M == 4
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GST v, , V0, C0, 0x00, V1, C1, 0x00
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.elseif \M == 2
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GST f, d, F0, C0, 0x00, F1, C1, 0x00
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.elseif \M == 1
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GST f, s, F0, C0, 0x00, F1, C1, 0x00
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.endif
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PTR_ALSL C0, LDC, C0, 1
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PTR_ALSL C1, LDC, C1, 1
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PTR_ADDI B_cur, B_cur, 8
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move A0, A
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.L_M\M\()_N1:
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andi N1, N, 0x01
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beqz N1, .L_M\M\()_END
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GXOR xv, v, D0, D0, D0
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move K1, K
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move X0, B_cur
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bge ZERO, K, .L_M\M\()_N1_END
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.L_M\M\()_N1_K1:
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PTR_ADDI K1, K1, -1
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GLD xv, , S0, A0, 0x00
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GLDREPL xv, w, Z0, X0, 0x00
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GMADD xvf, s, D0, S0, Z0, D0
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PTR_ADD X0, X0, LDB
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PTR_ADD A0, A0, LDA
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bnez K1, .L_M\M\()_N1_K1
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.L_M\M\()_N1_END:
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GMUL xvf, s, D0, D0, VALPHA
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#ifndef B0
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GLD xv, , S0, C0, 0x00
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GMADD xvf, s, D0, S0, VBETA, D0
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#endif
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.if \M == 8
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GST xv, , D0, C0, 0x00
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.elseif \M == 4
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GST v, , V0, C0, 0x00
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.elseif \M == 2
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GST f, d, F0, C0, 0x00
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.elseif \M == 1
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GST f, s, F0, C0, 0x00
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.endif
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.L_M\M\()_END:
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.if \M == 8
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PTR_ADDI A, A, 0x20
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PTR_ADDI C, C, 0x20
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.elseif \M == 4
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PTR_ADDI A, A, 0x10
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PTR_ADDI C, C, 0x10
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.elseif \M == 2
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PTR_ADDI A, A, 0x08
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PTR_ADDI C, C, 0x08
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.elseif \M == 1
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PTR_ADDI A, A, 0x04
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PTR_ADDI C, C, 0x04
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.endif
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.endm
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PROLOGUE
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PTR_LD LDC, $sp, 0
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push_if_used 5, 2
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xvreplve0.w VALPHA, VALPHA
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#ifndef B0
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xvreplve0.w VBETA, VBETA
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#endif
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PTR_SLLI LDA, LDA, 2
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PTR_SLLI LDB, LDB, 2
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PTR_SLLI LDC, LDC, 2
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PTR_SRAI M32, M, 5
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beqz M32, .L_M31
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.L_M32:
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PTR_SRAI N4, N, 2
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move A0, A
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move B_cur, B // Reset B to origin for each M block
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move C0, C
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PTR_ADD C1, C0, LDC
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PTR_ADD C2, C1, LDC
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PTR_ADD C3, C2, LDC
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beqz N4, .L_M32_N3
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.L_M32_N4:
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GXOR xv, v, D0, D0, D0, D1, D1, D1, D2, D2, D2, D3, D3, D3, \
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D4, D4, D4, D5, D5, D5, D6, D6, D6, D7, D7, D7, \
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D8, D8, D8, D9, D9, D9, D10, D10, D10, D11, D11, D11, \
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D12, D12, D12, D13, D13, D13, D14, D14, D14, D15, D15, D15
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move K1, K
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move X0, B_cur
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PTR_ADDI N4, N4, -1
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bge ZERO, K, .L_M32_N4_END
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.L_M32_N4_K1:
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PTR_ADDI K1, K1, -1
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GLD xv, , S0, A0, 0x00, S1, A0, 0x20, S2, A0, 0x40, S3, A0, 0x60
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GLDREPL xv, w, Z0, X0, 0x00, Z1, X0, 0x04, Z2, X0, 0x08, Z3, X0, 0x0C
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GMADD xvf, s, D0, S0, Z0, D0, D1, S1, Z0, D1, D2, S2, Z0, D2, D3, S3, Z0, D3, \
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D4, S0, Z1, D4, D5, S1, Z1, D5, D6, S2, Z1, D6, D7, S3, Z1, D7, \
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D8, S0, Z2, D8, D9, S1, Z2, D9, D10, S2, Z2, D10, D11, S3, Z2, D11, \
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D12, S0, Z3, D12, D13, S1, Z3, D13, D14, S2, Z3, D14, D15, S3, Z3, D15
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PTR_ADD X0, X0, LDB
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PTR_ADD A0, A0, LDA
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bnez K1, .L_M32_N4_K1
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.L_M32_N4_END:
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GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA, D2, D2, VALPHA, D3, D3, VALPHA, \
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D4, D4, VALPHA, D5, D5, VALPHA, D6, D6, VALPHA, D7, D7, VALPHA, \
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D8, D8, VALPHA, D9, D9, VALPHA, D10, D10, VALPHA, D11, D11, VALPHA, \
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D12, D12, VALPHA, D13, D13, VALPHA, D14, D14, VALPHA, D15, D15, VALPHA
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#ifndef B0
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GLD xv, , S0, C0, 0x00, S1, C0, 0x20, S2, C0, 0x40, S3, C0, 0x60
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GMADD xvf, s, D0, S0, VBETA, D0, D1, S1, VBETA, D1, D2, S2, VBETA, D2, D3, S3, VBETA, D3
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GLD xv, , S0, C1, 0x00, S1, C1, 0x20, S2, C1, 0x40, S3, C1, 0x60
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GMADD xvf, s, D4, S0, VBETA, D4, D5, S1, VBETA, D5, D6, S2, VBETA, D6, D7, S3, VBETA, D7
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GLD xv, , S0, C2, 0x00, S1, C2, 0x20, S2, C2, 0x40, S3, C2, 0x60
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GMADD xvf, s, D8, S0, VBETA, D8, D9, S1, VBETA, D9, D10, S2, VBETA, D10, D11, S3, VBETA, D11
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GLD xv, , S0, C3, 0x00, S1, C3, 0x20, S2, C3, 0x40, S3, C3, 0x60
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GMADD xvf, s, D12, S0, VBETA, D12, D13, S1, VBETA, D13, D14, S2, VBETA, D14, D15, S3, VBETA, D15
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#endif
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GST xv, , D12, C3, 0x00, D13, C3, 0x20, D14, C3, 0x40, D15, C3, 0x60, \
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D8, C2, 0x00, D9, C2, 0x20, D10, C2, 0x40, D11, C2, 0x60, \
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D4, C1, 0x00, D5, C1, 0x20, D6, C1, 0x40, D7, C1, 0x60, \
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D0, C0, 0x00, D1, C0, 0x20, D2, C0, 0x40, D3, C0, 0x60
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PTR_ALSL C0, LDC, C0, 2
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PTR_ALSL C1, LDC, C1, 2
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PTR_ALSL C2, LDC, C2, 2
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PTR_ALSL C3, LDC, C3, 2
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PTR_ADDI B_cur, B_cur, 16 // Advance B along N by 4 words
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move A0, A
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bnez N4, .L_M32_N4
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.L_M32_N3:
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andi N2, N, 0x02
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beqz N2, .L_M32_N1
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.L_M32_N2:
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GXOR xv, v, D0, D0, D0, D1, D1, D1, D2, D2, D2, D3, D3, D3, \
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D4, D4, D4, D5, D5, D5, D6, D6, D6, D7, D7, D7
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move K1, K
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move X0, B_cur
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bge ZERO, K, .L_M32_N2_END
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.L_M32_N2_K1:
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PTR_ADDI K1, K1, -1
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GLD xv, , S0, A0, 0x00, S1, A0, 0x20, S2, A0, 0x40, S3, A0, 0x60
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GLDREPL xv, w, Z0, X0, 0x00, Z1, X0, 0x04
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GMADD xvf, s, D0, S0, Z0, D0, D1, S1, Z0, D1, D2, S2, Z0, D2, D3, S3, Z0, D3, \
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D4, S0, Z1, D4, D5, S1, Z1, D5, D6, S2, Z1, D6, D7, S3, Z1, D7
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PTR_ADD X0, X0, LDB
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PTR_ADD A0, A0, LDA
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bnez K1, .L_M32_N2_K1
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.L_M32_N2_END:
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GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA, D2, D2, VALPHA, D3, D3, VALPHA, \
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D4, D4, VALPHA, D5, D5, VALPHA, D6, D6, VALPHA, D7, D7, VALPHA
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#ifndef B0
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GLD xv, , S0, C0, 0x00, S1, C0, 0x20, S2, C0, 0x40, S3, C0, 0x60
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GMADD xvf, s, D0, S0, VBETA, D0, D1, S1, VBETA, D1, D2, S2, VBETA, D2, D3, S3, VBETA, D3
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GLD xv, , S0, C1, 0x00, S1, C1, 0x20, S2, C1, 0x40, S3, C1, 0x60
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GMADD xvf, s, D4, S0, VBETA, D4, D5, S1, VBETA, D5, D6, S2, VBETA, D6, D7, S3, VBETA, D7
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#endif
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GST xv, , D4, C1, 0x00, D5, C1, 0x20, D6, C1, 0x40, D7, C1, 0x60, \
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D0, C0, 0x00, D1, C0, 0x20, D2, C0, 0x40, D3, C0, 0x60
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PTR_ALSL C0, LDC, C0, 1
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PTR_ALSL C1, LDC, C1, 1
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PTR_ADDI B_cur, B_cur, 8
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move A0, A
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.L_M32_N1:
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andi N1, N, 0x01
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beqz N1, .L_M32_END
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GXOR xv, v, D0, D0, D0, D1, D1, D1, D2, D2, D2, D3, D3, D3
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move K1, K
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move X0, B_cur
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bge ZERO, K, .L_M32_N1_END
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.L_M32_N1_K1:
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PTR_ADDI K1, K1, -1
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GLD xv, , S0, A0, 0x00, S1, A0, 0x20, S2, A0, 0x40, S3, A0, 0x60
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GLDREPL xv, w, Z0, X0, 0x00
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GMADD xvf, s, D0, S0, Z0, D0, D1, S1, Z0, D1, D2, S2, Z0, D2, D3, S3, Z0, D3
|
|
PTR_ADD X0, X0, LDB
|
|
PTR_ADD A0, A0, LDA
|
|
bnez K1, .L_M32_N1_K1
|
|
.L_M32_N1_END:
|
|
GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA, D2, D2, VALPHA, D3, D3, VALPHA
|
|
#ifndef B0
|
|
GLD xv, , S0, C0, 0x00, S1, C0, 0x20, S2, C0, 0x40, S3, C0, 0x60
|
|
GMADD xvf, s, D0, S0, VBETA, D0, D1, S1, VBETA, D1, D2, S2, VBETA, D2, D3, S3, VBETA, D3
|
|
#endif
|
|
GST xv, , D0, C0, 0x00, D1, C0, 0x20, D2, C0, 0x40, D3, C0, 0x60
|
|
PTR_ALSL C0, LDC, C0, 2
|
|
PTR_ADDI B_cur, B_cur, 4
|
|
move A0, A
|
|
.L_M32_END:
|
|
PTR_ADDI M32, M32, -1
|
|
PTR_ADDI A, A, 0x80
|
|
PTR_ADDI C, C, 0x80
|
|
bnez M32, .L_M32
|
|
.L_M31:
|
|
andi M16, M, 0x10
|
|
beqz M16, .L_M15
|
|
.L_M16:
|
|
PTR_SRAI N4, N, 2
|
|
move A0, A
|
|
move B_cur, B
|
|
move C0, C
|
|
PTR_ADD C1, C0, LDC
|
|
PTR_ADD C2, C1, LDC
|
|
PTR_ADD C3, C2, LDC
|
|
beqz N4, .L_M16_N3
|
|
.L_M16_N4:
|
|
GXOR xv, v, D0, D0, D0, D1, D1, D1, D2, D2, D2, D3, D3, D3, \
|
|
D4, D4, D4, D5, D5, D5, D6, D6, D6, D7, D7, D7
|
|
move K1, K
|
|
move X0, B_cur
|
|
PTR_ADDI N4, N4, -1
|
|
bge ZERO, K, .L_M16_N4_END
|
|
.L_M16_N4_K1:
|
|
PTR_ADDI K1, K1, -1
|
|
GLD xv, , S0, A0, 0x00, S1, A0, 0x20
|
|
GLDREPL xv, w, Z0, X0, 0x00, Z1, X0, 0x04, Z2, X0, 0x08, Z3, X0, 0x0C
|
|
GMADD xvf, s, D0, S0, Z0, D0, D1, S1, Z0, D1, \
|
|
D2, S0, Z1, D2, D3, S1, Z1, D3, \
|
|
D4, S0, Z2, D4, D5, S1, Z2, D5, \
|
|
D6, S0, Z3, D6, D7, S1, Z3, D7
|
|
PTR_ADD X0, X0, LDB
|
|
PTR_ADD A0, A0, LDA
|
|
bnez K1, .L_M16_N4_K1
|
|
.L_M16_N4_END:
|
|
GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA, D2, D2, VALPHA, D3, D3, VALPHA, \
|
|
D4, D4, VALPHA, D5, D5, VALPHA, D6, D6, VALPHA, D7, D7, VALPHA
|
|
#ifndef B0
|
|
GLD xv, , S0, C0, 0x00, S1, C0, 0x20
|
|
GMADD xvf, s, D0, S0, VBETA, D0, D1, S1, VBETA, D1
|
|
GLD xv, , S0, C1, 0x00, S1, C1, 0x20
|
|
GMADD xvf, s, D2, S0, VBETA, D2, D3, S1, VBETA, D3
|
|
GLD xv, , S0, C2, 0x00, S1, C2, 0x20
|
|
GMADD xvf, s, D4, S0, VBETA, D4, D5, S1, VBETA, D5
|
|
GLD xv, , S0, C3, 0x00, S1, C3, 0x20
|
|
GMADD xvf, s, D6, S0, VBETA, D6, D7, S1, VBETA, D7
|
|
#endif
|
|
GST xv, , D4, C2, 0x00, D5, C2, 0x20, D6, C3, 0x00, D7, C3, 0x20, \
|
|
D0, C0, 0x00, D1, C0, 0x20, D2, C1, 0x00, D3, C1, 0x20
|
|
PTR_ALSL C0, LDC, C0, 2
|
|
PTR_ALSL C1, LDC, C1, 2
|
|
PTR_ALSL C2, LDC, C2, 2
|
|
PTR_ALSL C3, LDC, C3, 2
|
|
PTR_ADDI B_cur, B_cur, 16
|
|
move A0, A
|
|
bnez N4, .L_M16_N4
|
|
.L_M16_N3:
|
|
andi N2, N, 0x02
|
|
beqz N2, .L_M16_N1
|
|
.L_M16_N2:
|
|
GXOR xv, v, D0, D0, D0, D1, D1, D1, D2, D2, D2, D3, D3, D3
|
|
move K1, K
|
|
move X0, B_cur
|
|
bge ZERO, K, .L_M16_N2_END
|
|
.L_M16_N2_K1:
|
|
PTR_ADDI K1, K1, -1
|
|
GLD xv, , S0, A0, 0x00, S1, A0, 0x20
|
|
GLDREPL xv, w, Z0, X0, 0x00, Z1, X0, 0x04
|
|
GMADD xvf, s, D0, S0, Z0, D0, D1, S1, Z0, D1, \
|
|
D2, S0, Z1, D2, D3, S1, Z1, D3
|
|
PTR_ADD X0, X0, LDB
|
|
PTR_ADD A0, A0, LDA
|
|
bnez K1, .L_M16_N2_K1
|
|
.L_M16_N2_END:
|
|
GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA, D2, D2, VALPHA, D3, D3, VALPHA
|
|
#ifndef B0
|
|
GLD xv, , S0, C0, 0x00, S1, C0, 0x20
|
|
GMADD xvf, s, D0, S0, VBETA, D0, D1, S1, VBETA, D1
|
|
GLD xv, , S0, C1, 0x00, S1, C1, 0x20
|
|
GMADD xvf, s, D2, S0, VBETA, D2, D3, S1, VBETA, D3
|
|
#endif
|
|
GST xv, , D0, C0, 0x00, D1, C0, 0x20, D2, C1, 0x00, D3, C1, 0x20
|
|
PTR_ALSL C0, LDC, C0, 1
|
|
PTR_ALSL C1, LDC, C1, 1
|
|
PTR_ADDI B_cur, B_cur, 8
|
|
move A0, A
|
|
.L_M16_N1:
|
|
andi N1, N, 0x01
|
|
beqz N1, .L_M16_END
|
|
GXOR xv, v, D0, D0, D0, D1, D1, D1
|
|
move K1, K
|
|
move X0, B_cur
|
|
bge ZERO, K, .L_M16_N1_END
|
|
.L_M16_N1_K1:
|
|
PTR_ADDI K1, K1, -1
|
|
GLD xv, , S0, A0, 0x00, S1, A0, 0x20
|
|
GLDREPL xv, w, Z0, X0, 0x00
|
|
GMADD xvf, s, D0, S0, Z0, D0, D1, S1, Z0, D1
|
|
PTR_ADD X0, X0, LDB
|
|
PTR_ADD A0, A0, LDA
|
|
bnez K1, .L_M16_N1_K1
|
|
.L_M16_N1_END:
|
|
GMUL xvf, s, D0, D0, VALPHA, D1, D1, VALPHA
|
|
#ifndef B0
|
|
GLD xv, , S0, C0, 0x00, S1, C0, 0x20
|
|
GMADD xvf, s, D0, S0, VBETA, D0, D1, S1, VBETA, D1
|
|
#endif
|
|
GST xv, , D0, C0, 0x00, D1, C0, 0x20
|
|
.L_M16_END:
|
|
PTR_ADDI A, A, 0x40
|
|
PTR_ADDI C, C, 0x40
|
|
.L_M15:
|
|
andi M8, M, 0x08
|
|
beqz M8, .L_M7
|
|
.L_M8:
|
|
SGEMM_SMALL_KERNEL_NT_TAIL 8
|
|
.L_M7:
|
|
andi M4, M, 0x04
|
|
beqz M4, .L_M3
|
|
.L_M4:
|
|
SGEMM_SMALL_KERNEL_NT_TAIL 4
|
|
.L_M3:
|
|
andi M2, M, 0x02
|
|
beqz M2, .L_M1
|
|
.L_M2:
|
|
SGEMM_SMALL_KERNEL_NT_TAIL 2
|
|
.L_M1:
|
|
andi M1, M, 0x01
|
|
beqz M1, .L_M0
|
|
SGEMM_SMALL_KERNEL_NT_TAIL 1
|
|
.L_M0:
|
|
pop_if_used 5, 2
|
|
jirl $r0, $r1, 0x0
|
|
EPILOGUE |