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OpenBLAS/driver
Hugo Meiland 269e1cd505 RISC-V: add get_L2_size() and blas_set_parameter() for cache-aware GEMM blocking
RISC-V was the only major architecture without a get_L2_size() /
blas_set_parameter() implementation, so the GEMM cache-blocking parameters
(P/Q/R) were fixed at compile time regardless of the actual L2 cache size.

Because the blocking is now derived from the L2 cache detected at runtime
rather than a fixed compile-time constant, future RISC-V cores - which are
arriving with progressively larger and more varied L2 caches - get more
optimal blocking automatically, and the port gains the same runtime-tuning
hook x86 and LoongArch already use.

This adds, under ARCH_RISCV64:

- get_L2_size(): reads the level-2 (unified) cache size from Linux sysfs
  (/sys/devices/system/cpu/cpu0/cache/index*/{level,size}); RISC-V has no
  architectural cache-size query like x86 CPUID or LoongArch CPUCFG. Falls
  back to 512 KB when sysfs is unavailable.

- blas_set_parameter(): scales each precision's packed-A dimension P from the
  detected L2. The base blocking and the reference cache size come from the
  active core's own param.h block (*_DEFAULT_P_BASE, RISCV_L2_REFERENCE_KB),
  so the function carries no core-specific constants and is a no-op for cores
  that do not opt in. Q and R keep their param.h defaults.

- driver/others/memory.c and common_macro.h: add ARCH_RISCV64 to the existing
  architecture lists that call blas_set_parameter() and declare the runtime
  parameter variables (sgemm_p, dgemm_p, ...).

- param.h RISCV64_ZVL256B: declares the per-core base blocking + reference and
  maps SGEMM/DGEMM/CGEMM/ZGEMM DEFAULT_P to the runtime variables for static
  builds; DYNAMIC_ARCH keeps the literals, since kernel/setparam-ref.c
  init_parameter() initialises the gotoblas table from these macros and
  blas_set_parameter() is not called on the dynamic path.

Only RISCV64_ZVL256B opts in so far; its base + reference are tuned on the
SpaceMiT X60, where a 512 KB L2 reproduces the stock blocking, so this is
performance-neutral on current hardware. Verified: a static RISCV64_ZVL256B
build reproduces the stock 128/128/16384 (SGEMM) and 64/128/8192 (DGEMM)
blocking; a DYNAMIC_ARCH build compiles cleanly (per-core setparam-ref objects
build without error); and get_L2_size() reads the correct size on both a
SpaceMiT X60 (512 KB L2) and a SiFive U74 / VisionFive 2 (2 MB L2).
2026-07-13 11:00:15 +02:00
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2025-10-16 10:00:41 -07:00