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OpenBLAS/kernel/riscv64
hmeiland a3620c264a Add U74 target with a 4x4 register-tiled GEMM kernel
The SiFive U74 (RV64GC; e.g. StarFive JH7110 / VisionFive 2) is a scalar,
in-order core with no RVV, so today it falls back to RISCV64_GENERIC whose
S/D GEMM uses the generic 2x2 C micro-kernel.

Per the U74 Core Complex Manual (Table 169) fmadd.d has a 7-cycle latency
at repeat rate 1 (fully pipelined). A 2x2 tile exposes only 4 independent
accumulator chains -- fewer than the FMA latency -- so the FP pipe stalls
on the accumulator dependency, and the 1:1 load:FMA ratio saturates the
single load/store pipe ("only one outstanding line fill", manual 8.2).

This adds a portable 4x4 GEMM micro-kernel and a dedicated U74 target:

- kernel/generic/gemmkernel_4x4.c: 16-accumulator 4x4 register tile. 16
  independent chains exceed the 7-cycle latency, and the load:FMA ratio
  drops to 1:2. 16 acc + 4 A + 4 B fit RV64G's 32 FP registers without
  spilling. Full 4/2/1 edge handling in both M and N.

- U74 target wiring: getarch.c (FORCE_U74, 32 KiB/64 B L1D, 2 MiB L2),
  param.h (S/D UNROLL 4/4; complex stays 2/2), kernel/riscv64/KERNEL.U74
  (S/D GEMM -> gemmkernel_4x4 + gemm_[nt]copy_4; S/D TRMM -> existing
  trmmkernel_4x4), Makefile.prebuild + Makefile.riscv64 (-mtune=sifive-u74),
  TargetList.txt, cpuid_riscv64.c.

The 4x4 kernel was verified numerically against a naive reference GEMM,
driven through the real gemm_tcopy_4 / gemm_ncopy_4 packing routines,
across 27,436 M/N/K x alpha combinations covering every 4/2/1 tail case:
worst absolute error 0.

Build with: make TARGET=U74
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