kernel/wasm/KERNEL is included after KERNEL.WASM128_GENERIC and unconditionally pointed S/D AXPY at RISC-V scalar axpy.c, so the x86_64 V_SIMD sources listed in the target file never ran. Add kernel/wasm/axpy.c for both precisions. Unit-stride y += da * x uses eight independent v128 lanes (32 floats / 16 doubles) with IEEE mul+add; remainder is one vector then scalar. Skip relaxed madd: AXPY is checked to machine epsilon, and putting it in the generic V_SIMD path previously slowed Level 1. Non-unit stride stays scalar (no WASM gather); inc==0 uses that path so y[0] += n * da * x[0]. Guard SAXPYKERNEL/DAXPYKERNEL with ifndef in KERNEL so the target file wins. CAXPY/ZAXPY stay RISC-V scalar. On n=512..8192 vs the RISC-V champion, SAXPY is about 1.4–3.0x and DAXPY about 1.4–2.2x. test.sh is green. Signed-off-by: Julien Jerphanion <git@jjerphan.xyz>
176 lines
5.6 KiB
C
176 lines
5.6 KiB
C
/***************************************************************************
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Copyright (c) 2026, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/*
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* WASM SIMD128 AXPY: y += da * x
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*
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* Compiled twice: SAXPY (-UDOUBLE) and DAXPY (-DDOUBLE). Unit-stride uses
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* eight independent v128 lanes (32 floats / 16 doubles) so load/mul/add/store
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* can overlap; remainder is one vector then scalar. IEEE mul+add (not
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* relaxed madd): AXPY is checked to machine epsilon, and relaxed madd in
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* the generic V_SIMD path previously slowed L1.
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*
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* Non-unit stride stays scalar (WASM SIMD128 has no gather). inc==0 is the
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* scalar path so y[0] += n * da * x[0] still holds.
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*/
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#include "common.h"
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#if defined(__wasm_simd128__)
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#include <wasm_simd128.h>
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#ifdef DOUBLE
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#define AXPY_VLEN 2
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#define AXPY_SPLAT wasm_f64x2_splat
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#define AXPY_MUL wasm_f64x2_mul
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#define AXPY_ADD wasm_f64x2_add
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#else
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#define AXPY_VLEN 4
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#define AXPY_SPLAT wasm_f32x4_splat
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#define AXPY_MUL wasm_f32x4_mul
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#define AXPY_ADD wasm_f32x4_add
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#endif
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#define AXPY_UNROLL 8
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#define AXPY_CHUNK (AXPY_VLEN * AXPY_UNROLL)
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#define AXPY_LOAD(p) wasm_v128_load((const void *)(p))
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#define AXPY_STORE(p, v) wasm_v128_store((void *)(p), (v))
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#define AXPY_MADD(y, a, x) AXPY_ADD((y), AXPY_MUL((a), (x)))
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static void axpy_kernel_unit(BLASLONG n, const FLOAT *x, FLOAT *y, FLOAT da) {
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const v128_t va = AXPY_SPLAT(da);
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BLASLONG i = 0;
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const BLASLONG n_main = n & ~(BLASLONG)(AXPY_CHUNK - 1);
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for (; i < n_main; i += AXPY_CHUNK) {
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v128_t x0 = AXPY_LOAD(x + i + 0 * AXPY_VLEN);
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v128_t x1 = AXPY_LOAD(x + i + 1 * AXPY_VLEN);
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v128_t x2 = AXPY_LOAD(x + i + 2 * AXPY_VLEN);
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v128_t x3 = AXPY_LOAD(x + i + 3 * AXPY_VLEN);
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v128_t x4 = AXPY_LOAD(x + i + 4 * AXPY_VLEN);
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v128_t x5 = AXPY_LOAD(x + i + 5 * AXPY_VLEN);
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v128_t x6 = AXPY_LOAD(x + i + 6 * AXPY_VLEN);
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v128_t x7 = AXPY_LOAD(x + i + 7 * AXPY_VLEN);
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v128_t y0 = AXPY_LOAD(y + i + 0 * AXPY_VLEN);
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v128_t y1 = AXPY_LOAD(y + i + 1 * AXPY_VLEN);
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v128_t y2 = AXPY_LOAD(y + i + 2 * AXPY_VLEN);
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v128_t y3 = AXPY_LOAD(y + i + 3 * AXPY_VLEN);
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v128_t y4 = AXPY_LOAD(y + i + 4 * AXPY_VLEN);
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v128_t y5 = AXPY_LOAD(y + i + 5 * AXPY_VLEN);
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v128_t y6 = AXPY_LOAD(y + i + 6 * AXPY_VLEN);
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v128_t y7 = AXPY_LOAD(y + i + 7 * AXPY_VLEN);
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AXPY_STORE(y + i + 0 * AXPY_VLEN, AXPY_MADD(y0, va, x0));
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AXPY_STORE(y + i + 1 * AXPY_VLEN, AXPY_MADD(y1, va, x1));
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AXPY_STORE(y + i + 2 * AXPY_VLEN, AXPY_MADD(y2, va, x2));
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AXPY_STORE(y + i + 3 * AXPY_VLEN, AXPY_MADD(y3, va, x3));
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AXPY_STORE(y + i + 4 * AXPY_VLEN, AXPY_MADD(y4, va, x4));
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AXPY_STORE(y + i + 5 * AXPY_VLEN, AXPY_MADD(y5, va, x5));
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AXPY_STORE(y + i + 6 * AXPY_VLEN, AXPY_MADD(y6, va, x6));
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AXPY_STORE(y + i + 7 * AXPY_VLEN, AXPY_MADD(y7, va, x7));
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}
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for (; i + AXPY_VLEN <= n; i += AXPY_VLEN) {
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v128_t yi = AXPY_LOAD(y + i);
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v128_t xi = AXPY_LOAD(x + i);
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AXPY_STORE(y + i, AXPY_MADD(yi, va, xi));
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}
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for (; i < n; i++)
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y[i] += da * x[i];
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}
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#undef AXPY_LOAD
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#undef AXPY_STORE
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#undef AXPY_MADD
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#undef AXPY_CHUNK
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#undef AXPY_UNROLL
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#undef AXPY_VLEN
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#undef AXPY_SPLAT
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#undef AXPY_MUL
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#undef AXPY_ADD
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#endif
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int CNAME(BLASLONG n, BLASLONG dummy0, BLASLONG dummy1, FLOAT da, FLOAT *x,
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BLASLONG inc_x, FLOAT *y, BLASLONG inc_y, FLOAT *dummy,
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BLASLONG dummy2) {
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BLASLONG i = 0;
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BLASLONG ix = 0, iy = 0;
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(void)dummy0;
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(void)dummy1;
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(void)dummy;
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(void)dummy2;
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if (n <= 0)
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return 0;
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if (da == 0.0)
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return 0;
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if ((inc_x == 1) && (inc_y == 1)) {
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#if defined(__wasm_simd128__)
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axpy_kernel_unit(n, x, y, da);
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#else
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while (i < n) {
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y[i] += da * x[i];
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i++;
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}
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#endif
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return 0;
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}
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{
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BLASLONG n1 = n & ~(BLASLONG)3;
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while (i < n1) {
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FLOAT m1 = da * x[ix];
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FLOAT m2 = da * x[ix + inc_x];
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FLOAT m3 = da * x[ix + 2 * inc_x];
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FLOAT m4 = da * x[ix + 3 * inc_x];
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y[iy] += m1;
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y[iy + inc_y] += m2;
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y[iy + 2 * inc_y] += m3;
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y[iy + 3 * inc_y] += m4;
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ix += inc_x * 4;
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iy += inc_y * 4;
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i += 4;
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}
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}
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while (i < n) {
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y[iy] += da * x[ix];
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ix += inc_x;
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iy += inc_y;
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i++;
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}
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return 0;
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}
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